Changeset 1450

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Timestamp:
02/11/06 13:04:39 (3 years ago)
Author:
svens
Message:

* Integrates new hal (0.9.16.6)

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  • trunk/ath/if_ath.c

    r1443 r1450  
    35473547        qi.tqi_cwmax = 0; 
    35483548#ifdef ATH_SUPERG_DYNTURBO 
    3549         qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 
     3549        qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 
    35503550#endif 
    35513551        /* NB: don't enable any interrupts */ 
    …… 
    59935993         */ 
    59945994        if (qtype == HAL_TX_QUEUE_UAPSD) 
    5995                 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 
     5995                qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 
    59965996        else 
    5997                 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE; 
     5997                qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 
    59985998        qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 
    59995999        if (qnum == -1) { 

  • trunk/hal/COPYRIGHT

    r1260 r1450  
    55 
    66/*- 
    7  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting, Atheros 
     7 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros 
    88 * Communications, Inc.  All rights reserved. 
    99 * 
    …… 
    3939 * SUCH DAMAGES. 
    4040 * 
    41  * $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/COPYRIGHT#4 $ 
     41 * $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/COPYRIGHT#5 $ 
    4242 */ 

  • trunk/hal/README

    r1260 r1450  
    1 $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/README#4 $ 
    2  
    3  
    4 WARNING: THIS IS A BETA DISTRIBUTION.  THIS SOFTWARE HAS KNOWN PROBLEMS AND 
    5 WARNING: LIMITATIONS THAT WILL BE CORRECTED BEFORE A PRODUCTION RELEASE. 
    6 WARNING: USE AT YOUR OWN RISK! 
     1$Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/README#5 $ 
    72 
    83 
    …… 
    105=================================== 
    116 
    12 * Copyright (c) 2002-2005 Sam Leffler. 
    13 * Copyright (c) 2002-2005 Atheros Communications, Inc. 
     7* Copyright (c) 2002-2006 Sam Leffler. 
     8* Copyright (c) 2002-2006 Atheros Communications, Inc. 
    149* All rights reserved. 
    1510 
    1611Read the file COPYRIGHT for the complete copyright. 
    1712 
    18 This code manages much of the chip-specific operation of the Atheros driver. 
    19 The HAL is provided in a binary-only form in order to comply with FCC 
    20 regulations.  In particular, a radio transmitter can only be operated at 
    21 power levels and on frequency channels for which it is approved.  The FCC 
    22 requires that a software-defined radio cannot be configured by a user 
    23 to operate outside the approved power levels and frequency channels. 
    24 This makes it difficult to open-source code that enforces limits on 
    25 the power levels, frequency channels and other parameters of the radio 
    26 transmitter.  See 
     13This code manages much of the chip-specific operation of the Atheros 
     14driver.  The HAL is provided in a binary-only form in order to 
     15comply with local regulatory agency rules.  In the United States 
     16the FCC requires that a radio transmitter only be operated at power 
     17levels and on frequency channels for which it is approved.  The FCC 
     18requires that a software-defined radio cannot be configured by a 
     19user to operate outside the approved power levels and frequency 
     20channels.  This makes it difficult to open-source code that enforces 
     21limits on the power levels, frequency channels and other parameters 
     22of the radio transmitter.  See 
    2723 
    2824http://ftp.fcc.gov/Bureaus/Engineering_Technology/Orders/2001/fcc01264.pdf 
    2925 
    30 for the specific FCC regulation.  Because the module is provided in a 
    31 binary-only form it is marked "Proprietary"; this means when you load 
    32 it you will see messages that your system is now "tainted". 
     26for the specific FCC regulation.  Because the module is provided 
     27in a binary-only form it is marked "Proprietary" on Linux; this 
     28means when you load it you will see messages that your system is 
     29now "tainted". 
    3330 
    3431If you wish to use this driver on a platform for which an ath_hal 
    …… 
    4037Atheros Hardware 
    4138================ 
    42 There are currently 3 generations of Atheros 802.11 wireless devices: 
     39There are many generations of Atheros 802.11 wireless devices that 
     40are typically referred to by their programming model: 
    4341 
    44425210    supports 11a only 
    …… 
    4745 
    4846These parts have been incorporated in a variety of retail products 
    49 including cardbus cards from DLink, Linksys, Netgear, and Proxim; and 
    50 mini-pci cards from some of these same vendors.  In addition many 
    51 laptop vendors use Atheros mini-pci cards for their builtin wireless 
    52 support.  An (incomplete) list of products that use Atheros parts is: 
     47including cardbus cards and mini-pci cards.  In addition many laptop 
     48vendors use Atheros mini-pci cards for their builtin wireless 
     49support. 
    5350 
    54 Netgear WAG511          D-Link DWL-AG520        Linksys WPC55AG 
    55 Netgear WAB501          D-Link DWL-AG650        Linksys WMP55AG 
    56                         D-Link DWL-AB650        Linksys WPC51AB 
    57  
    58 In general, if a device is identified as ``11a only'' it is almost 
    59 certain to contain an Atheros 5210 part in it.  All retail a+b 
    60 products use the 5211.  The latest generation of universal a+b+g 
    61 combo products use the 5212.  When in doubt check the PCI vendor 
    62 id with a tool like lspci, the Atheros vendor id is 0x168c; e.g. 
    63  
    64    00:13.0 Ethernet controller: Unknown device 168c:0012 (rev 01) 
     51The Atheors PCI vendor id is 0x168c.  The file ah_devid.h lists most 
     52known PCI device id's but is not exhaustive.  Some vendors program 
     53their own vendor and/or device id's to aid in BIOS-locking mini-pci 
     54cards in laptops. 

  • trunk/hal/ah.h

    r1441 r1450  
    11/*- 
    2  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting, Atheros 
     2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros 
    33 * Communications, Inc.  All rights reserved. 
    44 * 
    …… 
    117117        HAL_CAP_TPC_ACK         = 26,   /* ack txpower with per-packet tpc */ 
    118118        HAL_CAP_TPC_CTS         = 27,   /* cts txpower with per-packet tpc */ 
     119        HAL_CAP_11D             = 28,   /* 11d beacon support for changing cc */ 
    119120} HAL_CAPABILITY_TYPE; 
    120121 
    …… 
    123124 * the possible 802.11 operational states and there may 
    124125 * be a many-to-one mapping between these states and the 
    125  * actual hardware states for the LED's (i.e. the hardware 
     126 * actual hardware state for the LED's (i.e. the hardware 
    126127 * may have fewer states). 
    127128 */ 
    …… 
    168169 */ 
    169170typedef enum { 
    170         TXQ_FLAG_TXOKINT_ENABLE     = 0x0001,    /* enable TXOK interrupt */ 
    171         TXQ_FLAG_TXERRINT_ENABLE    = 0x0001,    /* enable TXERR interrupt */ 
    172         TXQ_FLAG_TXDESCINT_ENABLE   = 0x0002,    /* enable TXDESC interrupt */ 
    173         TXQ_FLAG_TXEOLINT_ENABLE    = 0x0004,    /* enable TXEOL interrupt */ 
    174         TXQ_FLAG_TXURNINT_ENABLE    = 0x0008,    /* enable TXURN interrupt */ 
    175         TXQ_FLAG_BACKOFF_DISABLE    = 0x0010,    /* disable Post Backoff  */ 
    176         TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,    /* compression enabled */ 
    177         TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, /* enable ready time 
    178                                                         expiry policy */ 
    179         TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, /* enable backoff while 
    180                                                         sending fragment burst*/ 
     171        /* 
     172         * Per queue interrupt enables.  When set the associated 
     173         * interrupt may be delivered for packets sent through 
     174         * the queue.  Without these enabled no interrupts will 
     175         * be delivered for transmits through the queue. 
     176         */ 
     177        HAL_TXQ_TXOKINT_ENABLE     = 0x0001,    /* enable TXOK interrupt */ 
     178        HAL_TXQ_TXERRINT_ENABLE    = 0x0001,    /* enable TXERR interrupt */ 
     179        HAL_TXQ_TXDESCINT_ENABLE   = 0x0002,    /* enable TXDESC interrupt */ 
     180        HAL_TXQ_TXEOLINT_ENABLE    = 0x0004,    /* enable TXEOL interrupt */ 
     181        HAL_TXQ_TXURNINT_ENABLE    = 0x0008,    /* enable TXURN interrupt */ 
     182        /* 
     183         * Enable hardware compression for packets sent through 
     184         * the queue.  The compression buffer must be setup and 
     185         * packets must have a key entry marked in the tx descriptor. 
     186         */ 
     187        HAL_TXQ_COMPRESSION_ENABLE  = 0x0010,   /* enable h/w compression */ 
     188        /* 
     189         * Disable queue when veol is hit or ready time expires. 
     190         * By default the queue is disabled only on reaching the 
     191         * physical end of queue (i.e. a null link ptr in the 
     192         * descriptor chain). 
     193         */ 
     194        HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 
     195        /* 
     196         * Schedule frames on delivery of a DBA (DMA Beacon Alert) 
     197         * event.  Frames will be transmitted only when this timer 
     198         * fires, e.g to transmit a beacon in ap or adhoc modes. 
     199         */ 
     200        HAL_TXQ_DBA_GATED           = 0x0040,   /* schedule based on DBA */ 
     201        /* 
     202         * Each transmit queue has a counter that is incremented 
     203         * each time the queue is enabled and decremented when 
     204         * the list of frames to transmit is traversed (or when 
     205         * the ready time for the queue expires).  This counter 
     206         * must be non-zero for frames to be scheduled for 
     207         * transmission.  The following controls disable bumping 
     208         * this counter under certain conditions.  Typically this 
     209         * is used to gate frames based on the contents of another 
     210         * queue (e.g. CAB traffic may only follow a beacon frame). 
     211         * These are meaningful only when frames are scheduled 
     212         * with a non-ASAP policy (e.g. DBA-gated). 
     213         */ 
     214        HAL_TXQ_CBR_DIS_QEMPTY      = 0x0080,   /* disable on this q empty */ 
     215        HAL_TXQ_CBR_DIS_BEMPTY      = 0x0100,   /* disable on beacon q empty */ 
     216 
     217        /* 
     218         * Fragment burst backoff policy.  Normally the no backoff 
     219         * is done after a successful transmission, the next fragment 
     220         * is sent at SIFS.  If this flag is set backoff is done 
     221         * after each fragment, regardless whether it was ack'd or 
     222         * not, after the backoff count reaches zero a normal channel 
     223         * access procedure is done before the next transmit (i.e. 
     224         * wait AIFS instead of SIFS). 
     225         */ 
     226        HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 
     227        /* 
     228         * Disable post-tx backoff following each frame. 
     229         */ 
     230        HAL_TXQ_BACKOFF_DISABLE     = 0x00010000, /* disable post backoff  */ 
     231        /* 
     232         * DCU arbiter lockout control.  This controls how 
     233         * lower priority tx queues are handled with respect to 
     234         * to a specific queue when multiple queues have frames 
     235         * to send.  No lockout means lower priority queues arbitrate 
     236         * concurrently with this queue.  Intra-frame lockout 
     237         * means lower priority queues are locked out until the 
     238         * current frame transmits (e.g. including backoffs and bursting). 
     239         * Global lockout means nothing lower can arbitrary so 
     240         * long as there is traffic activity on this queue (frames, 
     241         * backoff, etc). 
     242         */ 
     243        HAL_TXQ_ARB_LOCKOUT_INTRA   = 0x00020000, /* intra-frame lockout */ 
     244        HAL_TXQ_ARB_LOCKOUT_GLOBAL  = 0x00040000, /* full lockout s */ 
     245 
     246        HAL_TXQ_IGNORE_VIRTCOL      = 0x00080000, /* ignore virt collisions */ 
     247        HAL_TXQ_SEQNUM_INC_DIS      = 0x00100000, /* disable seqnum increment */ 
    181248} HAL_TX_QUEUE_FLAGS; 
    182249 
    183250typedef struct { 
    184         u_int32_t tqi_ver;            /* hal TXQ version */ 
     251        u_int32_t      tqi_ver;               /* hal TXQ version */ 
    185252        HAL_TX_QUEUE_SUBTYPE tqi_subtype;       /* subtype if applicable */ 
    186         HAL_TX_QUEUE_FLAGS tqi_qflags;  /* flags (see above) */ 
    187         u_int32_t tqi_priority;               /* (not used) */ 
    188         u_int32_t tqi_aifs;           /* aifs */ 
    189         u_int32_t tqi_cwmin;          /* cwMin */ 
    190         u_int32_t tqi_cwmax;          /* cwMax */ 
    191         u_int16_t tqi_shretry;                /* rts retry limit */ 
    192         u_int16_t tqi_lgretry;                /* long retry limit (not used)*/ 
    193         u_int32_t tqi_cbrPeriod; 
    194         u_int32_t tqi_cbrOverflowLimit; 
    195         u_int32_t tqi_burstTime; 
    196         u_int32_t tqi_readyTime; 
    197         u_int32_t tqi_compBuf;                 /* compression buffer phys addr */ 
     253        HAL_TX_QUEUE_FLAGS tqi_qflags;         /* flags (see above) */ 
     254        u_int32_t      tqi_priority;          /* (not used) */ 
     255        u_int32_t      tqi_aifs;              /* aifs */ 
     256        u_int32_t      tqi_cwmin;             /* cwMin */ 
     257        u_int32_t      tqi_cwmax;             /* cwMax */ 
     258        u_int16_t      tqi_shretry;           /* rts retry limit */ 
     259        u_int16_t      tqi_lgretry;           /* long retry limit (not used)*/ 
     260        u_int32_t      tqi_cbrPeriod;          /* CBR period (us) */ 
     261        u_int32_t      tqi_cbrOverflowLimit;   /* threshold for CBROVF int */ 
     262        u_int32_t      tqi_burstTime;          /* max burst duration (us) */ 
     263        u_int32_t      tqi_readyTime;          /* frame schedule time (us) */ 
     264        u_int32_t      tqi_compBuf;            /* comp buffer phys addr */ 
    198265} HAL_TXQ_INFO; 
    199266 
     267#define HAL_TQI_NONVAL 0xffff 
     268 
    200269/* token to use for aifs, cwmin, cwmax */ 
    201 #define HAL_TXQ_USEDEFAULT      ((u_int32_t) - 1) 
     270#define HAL_TXQ_USEDEFAULT      ((u_int32_t) -1) 
    202271 
    203272/* compression definitions */ 
    …… 
    308377 */ 
    309378typedef struct { 
    310         u_int16_t channel;            /* setting in Mhz */ 
    311         u_int16_t channelFlags;               /* see below */ 
    312         u_int8_t privFlags; 
    313         int8_t maxRegTxPower;         /* max regulatory tx power in dBm */ 
    314         int8_t maxTxPower;            /* max true tx power in 0.25 dBm */ 
    315         int8_t minTxPower;            /* min true tx power in 0.25 dBm */ 
     379        u_int16_t      channel;       /* setting in Mhz */ 
     380        u_int16_t      channelFlags;  /* see below */ 
     381        u_int8_t       privFlags; 
     382        int8_t         maxRegTxPower; /* max regulatory tx power in dBm */ 
     383        int8_t         maxTxPower;    /* max true tx power in 0.25 dBm */ 
     384        int8_t         minTxPower;    /* min true tx power in 0.25 dBm */ 
    316385} HAL_CHANNEL; 
    317386 
    …… 
    361430 
    362431typedef struct { 
    363         u_int32_t ackrcv_bad; 
    364         u_int32_t rts_bad; 
    365         u_int32_t rts_good; 
    366         u_int32_t fcs_bad; 
    367         u_int32_t beacons; 
     432        u_int32_t      ackrcv_bad; 
     433        u_int32_t      rts_bad; 
     434        u_int32_t      rts_good; 
     435        u_int32_t      fcs_bad; 
     436        u_int32_t      beacons; 
    368437} HAL_MIB_STATS; 
    369438 
    …… 
    395464 
    396465typedef struct { 
    397         int rateCount;                        /* NB: for proper padding */ 
    398         u_int8_t        rateCodeToIndex[32];           /* back mapping */ 
     466        int            rateCount;             /* NB: for proper padding */ 
     467        u_int8_t        rateCodeToIndex[32];    /* back mapping */ 
    399468        struct { 
    400                 u_int8_t valid;                       /* valid for rate control use */ 
    401                 u_int8_t phy;                 /* CCK/OFDM/XR */ 
    402                 u_int16_t rateKbps;           /* transfer rate in kbs */ 
    403                 u_int8_t rateCode;            /* rate for h/w descriptors */ 
    404                 u_int8_t shortPreamble;               /* mask for enabling short 
     469                u_int8_t       valid;         /* valid for rate control use */ 
     470                u_int8_t       phy;           /* CCK/OFDM/XR */ 
     471                u_int16_t      rateKbps;      /* transfer rate in kbs */ 
     472                u_int8_t       rateCode;      /* rate for h/w descriptors */ 
     473                u_int8_t       shortPreamble; /* mask for enabling short 
    405474                                                 * preamble in CCK rate code */ 
    406                 u_int8_t dot11Rate;           /* value for supported rates 
     475                u_int8_t       dot11Rate;     /* value for supported rates 
    407476                                                 * info element of MLME */ 
    408                 u_int8_t controlRate;         /* index of next lower basic 
     477                u_int8_t       controlRate;   /* index of next lower basic 
    409478                                                 * rate; used for dur. calcs */ 
    410                 u_int16_t lpAckDuration;              /* long preamble ACK duration */ 
    411                 u_int16_t spAckDuration;              /* short preamble ACK duration*/ 
     479                u_int16_t      lpAckDuration; /* long preamble ACK duration */ 
     480                u_int16_t      spAckDuration; /* short preamble ACK duration*/ 
    412481        } info[32]; 
    413482} HAL_RATE_TABLE; 
    414483 
    415484typedef struct { 
    416         u_int rs_count;                               /* number of valid entries */ 
    417         u_int8_t rs_rates[32];                /* rates */ 
     485        u_int          rs_count;              /* number of valid entries */ 
     486        u_int8_t       rs_rates[32];          /* rates */ 
    418487} HAL_RATE_SET; 
    419488 
    …… 
    432501 
    433502typedef struct { 
    434         u_int8_t kv_type;             /* one of HAL_CIPHER */ 
    435         u_int8_t kv_pad; 
    436         u_int16_t kv_len;             /* length in bits */ 
    437         u_int8_t kv_val[16];          /* enough for 128-bit keys */ 
    438         u_int8_t kv_mic[8];           /* TKIP MIC key */ 
     503        u_int8_t       kv_type;               /* one of HAL_CIPHER */ 
     504        u_int8_t       kv_pad; 
     505        u_int16_t      kv_len;                /* length in bits */ 
     506        u_int8_t       kv_val[16];            /* enough for 128-bit keys */ 
     507        u_int8_t       kv_mic[8];             /* TKIP MIC key */ 
    439508} HAL_KEYVAL; 
    440509 
    …… 
    463532 */ 
    464533typedef struct { 
    465         u_int32_t bs_nexttbtt;                /* next beacon in TU */ 
    466         u_int32_t bs_nextdtim;                /* next DTIM in TU */ 
    467         u_int32_t bs_intval;                  /* beacon interval+flags */ 
     534        u_int32_t      bs_nexttbtt;           /* next beacon in TU */ 
     535        u_int32_t      bs_nextdtim;           /* next DTIM in TU */ 
     536        u_int32_t      bs_intval;             /* beacon interval+flags */ 
    468537#define HAL_BEACON_PERIOD       0x0000ffff      /* beacon interval period */ 
    469538#define HAL_BEACON_ENA          0x00800000      /* beacon xmit enable */ 
    470539#define HAL_BEACON_RESET_TSF    0x01000000      /* clear TSF */ 
    471         u_int32_t bs_dtimperiod; 
    472         u_int16_t bs_cfpperiod;                       /* CFP period in TU */ 
    473         u_int16_t bs_cfpmaxduration;          /* max CFP duration in TU */ 
    474         u_int32_t bs_cfpnext;                 /* next CFP in TU */ 
    475         u_int16_t bs_timoffset;                       /* byte offset to TIM bitmap */ 
    476         u_int16_t bs_bmissthreshold;          /* beacon miss threshold */ 
    477         u_int32_t bs_sleepduration;           /* max sleep duration */ 
     540        u_int32_t      bs_dtimperiod; 
     541        u_int16_t      bs_cfpperiod;          /* CFP period in TU */ 
     542        u_int16_t      bs_cfpmaxduration;     /* max CFP duration in TU */ 
     543        u_int32_t      bs_cfpnext;            /* next CFP in TU */ 
     544        u_int16_t      bs_timoffset;          /* byte offset to TIM bitmap */ 
     545        u_int16_t      bs_bmissthreshold;     /* beacon miss threshold */ 
     546        u_int32_t      bs_sleepduration;      /* max sleep duration */ 
    478547} HAL_BEACON_STATE; 
    479548 
    …… 
    483552 */ 
    484553typedef struct { 
    485         u_int32_t ns_avgbrssi;                /* average beacon rssi */ 
    486         u_int32_t ns_avgrssi;                 /* average data rssi */ 
    487         u_int32_t ns_avgtxrssi;                       /* average tx rssi */ 
     554        u_int32_t      ns_avgbrssi;   /* average beacon rssi */ 
     555        u_int32_t      ns_avgrssi;    /* average data rssi */ 
     556        u_int32_t      ns_avgtxrssi;  /* average tx rssi */ 
    488557} HAL_NODE_STATS; 
    489558 
    490 #define HAL_RSSI_EP_MULTIPLIER  (1 << 7)      /* pow2 to optimize out * and / */ 
     559#define HAL_RSSI_EP_MULTIPLIER  (1<<7)        /* pow2 to optimize out * and / */ 
    491560 
    492561struct ath_desc; 
    …… 
    503572 */ 
    504573struct ath_hal { 
    505         u_int32_t ah_magic;           /* consistency check magic number */ 
    506         u_int32_t ah_abi;             /* HAL ABI version */ 
    507 #define HAL_ABI_VERSION 0x05120700    /* YYMMDDnn */ 
    508         u_int16_t ah_devid;           /* PCI device ID */ 
    509         u_int16_t ah_subvendorid;     /* PCI subvendor ID */ 
    510         HAL_SOFTC ah_sc;                      /* back pointer to driver/os state */ 
    511         HAL_BUS_TAG ah_st;            /* params for register r+w */ 
    512         HAL_BUS_HANDLE ah_sh; 
    513         HAL_CTRY_CODE ah_countryCode; 
    514  
    515         u_int32_t ah_macVersion;              /* MAC version id */ 
    516         u_int16_t ah_macRev;          /* MAC revision */ 
    517         u_int16_t ah_phyRev;          /* PHY revision */ 
     574        u_int32_t      ah_magic;      /* consistency check magic number */ 
     575        u_int32_t      ah_abi;                /* HAL ABI version */ 
     576#define HAL_ABI_VERSION 0x05122200    /* YYMMDDnn */ 
     577        u_int16_t      ah_devid;      /* PCI device ID */ 
     578        u_int16_t      ah_subvendorid;        /* PCI subvendor ID */ 
     579        HAL_SOFTC      ah_sc;         /* back pointer to driver/os state */ 
     580        HAL_BUS_TAG    ah_st;         /* params for register r+w */ 
     581        HAL_BUS_HANDLE ah_sh; 
     582        HAL_CTRY_CODE  ah_countryCode; 
     583 
     584        u_int32_t      ah_macVersion; /* MAC version id */ 
     585        u_int16_t      ah_macRev;     /* MAC revision */ 
     586        u_int16_t      ah_phyRev;     /* PHY revision */ 
    518587        /* NB: when only one radio is present the rev is in 5Ghz */ 
    519         u_int16_t ah_analog5GhzRev;     /* 5GHz radio revision */ 
    520         u_int16_t ah_analog2GhzRev;     /* 2GHz radio revision */ 
    521         u_int8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; /* decomp mask array */ 
    522         const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, u_int); 
    523         void __ahdecl(*ah_detach)(struct ath_hal *); 
     588        u_int16_t       ah_analog5GhzRev;/* 5GHz radio revision */ 
     589        u_int16_t       ah_analog2GhzRev;/* 2GHz radio revision */ 
     590        u_int8_t        ah_decompMask[HAL_DECOMP_MASK_SIZE]; /* decomp mask array */ 
     591        const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 
     592                                u_int mode); 
     593        void      __ahdecl(*ah_detach)(struct ath_hal*); 
    524594 
    525595        /* Reset functions */ 
    526         HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, HAL_CHANNEL *, 
    527                 HAL_BOOL, HAL_STATUS *); 
    528         HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 
    529         void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 
    530         HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal *, HAL_CHANNEL *, 
    531                 HAL_BOOL *); 
    532         HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, u_int32_t); 
    533  
    534         void __ahdecl(*ah_arEnable)(struct ath_hal *); 
    535         void __ahdecl(*ah_arDisable)(struct ath_hal *); 
    536         void __ahdecl(*ah_arReset)(struct ath_hal *); 
    537         HAL_BOOL __ahdecl(*ah_radarHaveEvent)(struct ath_hal *); 
    538         HAL_BOOL __ahdecl(*ah_processDfs)(struct ath_hal *, HAL_CHANNEL *); 
    539         u_int32_t __ahdecl(*ah_dfsNolCheck)(struct ath_hal *, HAL_CHANNEL *, 
    540                 u_int32_t); 
    541         HAL_BOOL __ahdecl(*ah_radarWait)(struct ath_hal *, HAL_CHANNEL *); 
     596        HAL_BOOL  __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 
     597                                HAL_CHANNEL *, HAL_BOOL bChannelChange, 
     598                                HAL_STATUS *status); 
     599        HAL_BOOL  __ahdecl(*ah_phyDisable)(struct ath_hal *); 
     600        void      __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 
     601        HAL_BOOL  __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *, HAL_BOOL *); 
     602        HAL_BOOL  __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, u_int32_t); 
     603 
     604        void      __ahdecl(*ah_arEnable)(struct ath_hal *); 
     605        void      __ahdecl(*ah_arDisable)(struct ath_hal *); 
     606        void      __ahdecl(*ah_arReset)(struct ath_hal *); 
     607        HAL_BOOL  __ahdecl(*ah_radarHaveEvent)(struct ath_hal *); 
     608        HAL_BOOL  __ahdecl(*ah_processDfs)(struct ath_hal *, HAL_CHANNEL *); 
     609        u_int32_t __ahdecl(*ah_dfsNolCheck)(struct ath_hal *, HAL_CHANNEL *, u_int32_t); 
     610        HAL_BOOL  __ahdecl(*ah_radarWait)(struct ath_hal *, HAL_CHANNEL *); 
    542611 
    543612        /* Transmit functions */ 
    544         HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal *, HAL_BOOL); 
    545         int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 
    546                 const HAL_TXQ_INFO *); 
    547         HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int,  
    548                 const HAL_TXQ_INFO *); 
    549         HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int,  
    550                 HAL_TXQ_INFO *); 
    551         HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *, u_int); 
    552         HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *, u_int); 
    553         u_int32_t __ahdecl(*ah_getTxDP)(struct ath_hal *, u_int); 
    554         HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal *, u_int, u_int32_t); 
    555         u_int32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int); 
    556         HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal *, u_int); 
    557         HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal *, u_int); 
    558         HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 
    559                 u_int, u_int, HAL_PKT_TYPE, u_int, u_int, u_int, u_int, u_int, 
    560                 u_int, u_int, u_int, u_int, u_int, u_int); 
    561         HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc *, 
    562                 u_int, u_int, u_int, u_int, u_int, u_int); 
    563         HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 
    564                 u_int, HAL_BOOL, HAL_BOOL, const struct ath_desc *); 
    565         HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, struct ath_desc *); 
    566         void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, u_int32_t *); 
    567         void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc *); 
     613        HAL_BOOL  __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 
     614                                HAL_BOOL incTrigLevel); 
     615        int       __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 
     616                                const HAL_TXQ_INFO *qInfo); 
     617        HAL_BOOL  __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q,  
     618                                const HAL_TXQ_INFO *qInfo); 
     619        HAL_BOOL  __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q,  
     620                                HAL_TXQ_INFO *qInfo); 
     621        HAL_BOOL  __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 
     622        HAL_BOOL  __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 
     623        u_int32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 
     624        HAL_BOOL  __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, u_int32_t txdp); 
     625        u_int32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 
     626        HAL_BOOL  __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 
     627        HAL_BOOL  __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 
     628        HAL_BOOL  __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 
     629                                u_int pktLen, u_int hdrLen, 
     630                                HAL_PKT_TYPE type, u_int txPower, 
     631                                u_int txRate0, u_int txTries0, 
     632                                u_int keyIx, u_int antMode, u_int flags, 
     633                                u_int rtsctsRate, u_int rtsctsDuration, 
     634                                u_int compicvLen, u_int compivLen, 
     635                                u_int comp); 
     636        HAL_BOOL  __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 
     637                                u_int txRate1, u_int txTries1, 
     638                                u_int txRate2, u_int txTries2, 
     639                                u_int txRate3, u_int txTries3); 
     640        HAL_BOOL  __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 
     641                                u_int segLen, HAL_BOOL firstSeg, 
     642                                HAL_BOOL lastSeg, const struct ath_desc *); 
     643        HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, struct ath_desc*); 
     644        void       __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, u_int32_t *); 
     645        void       __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 
    568646 
    569647        /* Receive Functions */ 
    570         u_int32_t __ahdecl(*ah_getRxDP)(struct ath_hal *); 
    571         void __ahdecl(*ah_setRxDP)(struct ath_hal *, u_int32_t); 
    572         void __ahdecl(*ah_enableReceive)(struct ath_hal *); 
    573         HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal *); 
    574         void __ahdecl(*ah_startPcuReceive)(struct ath_hal *); 
    575         void __ahdecl(*ah_stopPcuReceive)(struct ath_hal *); 
    576         void __ahdecl(*ah_setMulticastFilter)(struct ath_hal *, u_int32_t, 
    577                 u_int32_t); 
    578         HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal *, u_int32_t); 
    579         HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal *, u_int32_t); 
    580         u_int32_t __ahdecl(*ah_getRxFilter)(struct ath_hal *); 
    581         void __ahdecl(*ah_setRxFilter)(struct ath_hal *, u_int32_t); 
    582         HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 
    583                 u_int32_t, u_int); 
     648        u_int32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 
     649        void      __ahdecl(*ah_setRxDP)(struct ath_hal*, u_int32_t rxdp); 
     650        void      __ahdecl(*ah_enableReceive)(struct ath_hal*); 
     651        HAL_BOOL  __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 
     652        void      __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 
     653        void      __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 
     654        void      __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 
     655                                u_int32_t filter0, u_int32_t filter1); 
     656        HAL_BOOL  __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 
     657                                u_int32_t index); 
     658        HAL_BOOL  __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 
     659                                u_int32_t index); 
     660        u_int32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 
     661        void      __ahdecl(*ah_setRxFilter)(struct ath_hal*, u_int32_t); 
     662        HAL_BOOL  __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 
     663                                u_int32_t size, u_int flags); 
    584664        HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *, 
    585                 u_int32_t, struct ath_desc *, u_int64_t); 
    586         void __ahdecl(*ah_rxMonitor)(struct ath_hal *, const HAL_NODE_STATS *, 
    587                 HAL_CHANNEL *); 
    588         void __ahdecl(*ah_procMibEvent)(struct ath_hal *, const HAL_NODE_STATS *); 
     665                                u_int32_t phyAddr, struct ath_desc *next, 
     666                                u_int64_t tsf); 
     667        void      __ahdecl(*ah_rxMonitor)(struct ath_hal *, 
     668                                const HAL_NODE_STATS *, HAL_CHANNEL *); 
     669        void      __ahdecl(*ah_procMibEvent)(struct ath_hal *, 
     670                                const HAL_NODE_STATS *); 
    589671 
    590672        /* Misc Functions */ 
    591673        HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 
    592                 HAL_CAPABILITY_TYPE, u_int32_t, u_int32_t *); 
    593         HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 
    594                 HAL_CAPABILITY_TYPE, u_int32_t, u_int32_t, HAL_STATUS *); 
    595         HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int, const void *, 
    596                 u_int32_t, void **, u_int32_t *); 
    597         void __ahdecl(*ah_getMacAddress)(struct ath_hal *, u_int8_t *); 
    598         HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const u_int8_t *); 
    599         void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, u_int8_t *); 
    600         HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const u_int8_t *); 
    601         HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal *, 
    602                 u_int16_t, HAL_STATUS *); 
    603         void __ahdecl(*ah_setLedState)(struct ath_hal *, HAL_LED_STATE); 
    604         void __ahdecl(*ah_writeAssocid)(struct ath_hal *, const u_int8_t *, 
    605                 u_int16_t); 
    606         HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, u_int32_t); 
    607         HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, u_int32_t); 
    608         u_int32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, u_int32_t); 
    609         HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,        u_int32_t, u_int32_t); 
    610         void __ahdecl(*ah_gpioSetIntr)(struct ath_hal *, u_int, u_int32_t); 
    611         u_int32_t __ahdecl(*ah_getTsf32)(struct ath_hal *); 
    612         u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal *); 
    613         void __ahdecl(*ah_resetTsf)(struct ath_hal *); 
    614         HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal *); 
    615         void __ahdecl(*ah_updateMibCounters)(struct ath_hal *, HAL_MIB_STATS *); 
    616         HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal *); 
    617         u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal *); 
    618         void __ahdecl(*ah_setDefAntenna)(struct ath_hal *, u_int); 
    619         HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal *, u_int); 
    620         u_int __ahdecl(*ah_getSlotTime)(struct ath_hal *); 
    621         HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal *, u_int); 
    622         u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal *); 
    623         HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal *, u_int); 
    624         u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal *); 
    625         HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal *, u_int16_t, int); 
    626         void __ahdecl(*ah_setCoverageClass)(struct ath_hal *, u_int8_t, int); 
     674                                HAL_CAPABILITY_TYPE, u_int32_t capability, 
     675                                u_int32_t *result); 
     676        HAL_BOOL   __ahdecl(*ah_setCapability)(struct ath_hal *, 
     677                                HAL_CAPABILITY_TYPE, u_int32_t capability, 
     678                                u_int32_t setting, HAL_STATUS *); 
     679        HAL_BOOL   __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 
     680                                const void *args, u_int32_t argsize, 
     681                                void **result, u_int32_t *resultsize); 
     682        void      __ahdecl(*ah_getMacAddress)(struct ath_hal *, u_int8_t *); 
     683        HAL_BOOL  __ahdecl(*ah_setMacAddress)(struct ath_hal *, const u_int8_t*); 
     684        void      __ahdecl(*ah_getBssIdMask)(struct ath_hal *, u_int8_t *); 
     685        HAL_BOOL  __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const u_int8_t*); 
     686        HAL_BOOL  __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 
     687                                u_int16_t, HAL_STATUS *); 
     688        void      __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 
     689        void      __ahdecl(*ah_writeAssocid)(struct ath_hal*, 
     690                                const u_int8_t *bssid, u_int16_t assocId); 
     691        HAL_BOOL  __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, u_int32_t gpio); 
     692        HAL_BOOL  __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, u_int32_t gpio); 
     693        u_int32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, u_int32_t gpio); 
     694        HAL_BOOL  __ahdecl(*ah_gpioSet)(struct ath_hal *, 
     695                                u_int32_t gpio, u_int32_t val); 
     696        void      __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, u_int32_t); 
     697        u_int32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 
     698        u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 
     699        void      __ahdecl(*ah_resetTsf)(struct ath_hal*); 
     700        HAL_BOOL  __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 
     701        void      __ahdecl(*ah_updateMibCounters)(struct ath_hal*,