Changeset 2365

Timestamp:

05/23/07 02:41:02 (2 years ago)

Author:

mentor

Message:

Formatting changes for r2363, r2364 and some previous code.

Files:

• branches/madwifi-old-openhal/openhal/ath5k_hw.c (modified) (112 diffs)

branches/madwifi-old-openhal/openhal/ath5k_hw.c

@@ -39 +39 @@
-         * From pcidevs_data.h
-         */
-PCI_PRODUCT_ATHEROS_AR5210,
-PCI_PRODUCT_ATHEROS_AR5210_AP,
-PCI_PRODUCT_ATHEROS_AR5210_DEFAULT,
-PCI_PRODUCT_ATHEROS_AR5211,
-PCI_PRODUCT_ATHEROS_AR5211_DEFAULT,
-PCI_PRODUCT_ATHEROS_AR5311,
-PCI_PRODUCT_ATHEROS_AR5211_FPGA11B,
-PCI_PRODUCT_ATHEROS_AR5211_LEGACY,
-PCI_PRODUCT_ATHEROS_AR5212,
-PCI_PRODUCT_ATHEROS_AR5212_DEFAULT,
-PCI_PRODUCT_ATHEROS_AR5212_FPGA,
-PCI_PRODUCT_ATHEROS_AR5212_IBM,
-     PCI_PRODUCT_3COM_3CRDAG675,
-    PCI_PRODUCT_3COM2_3CRPAG175,
-PCI_PRODUCT_ATHEROS_AR5212_REV2,
-PCI_PRODUCT_ATHEROS_AR5212_REV7,
-PCI_PRODUCT_ATHEROS_AR5212_REV8,
-PCI_PRODUCT_ATHEROS_AR5212_0014,
-PCI_PRODUCT_ATHEROS_AR5212_0015,
-PCI_PRODUCT_ATHEROS_AR5212_0016,
-PCI_PRODUCT_ATHEROS_AR5212_0017,
-PCI_PRODUCT_ATHEROS_AR5212_0018,
-PCI_PRODUCT_ATHEROS_AR5212_0019,
-PCI_PRODUCT_ATHEROS_AR2413,
-PCI_PRODUCT_ATHEROS_AR5413,
-PCI_PRODUCT_ATHEROS_AR5424,
+ PCI_PRODUCT_ATHEROS_AR5210,             
+ PCI_PRODUCT_ATHEROS_AR5210_AP,          
+ PCI_PRODUCT_ATHEROS_AR5210_DEFAULT,     
+  PCI_PRODUCT_ATHEROS_AR5211,     
+  PCI_PRODUCT_ATHEROS_AR5211_DEFAULT,     
+  PCI_PRODUCT_ATHEROS_AR5311,     
+  PCI_PRODUCT_ATHEROS_AR5211_FPGA11B,     
+  PCI_PRODUCT_ATHEROS_AR5211_LEGACY, 
+  PCI_PRODUCT_ATHEROS_AR5212,     
+  PCI_PRODUCT_ATHEROS_AR5212_DEFAULT,     
+  PCI_PRODUCT_ATHEROS_AR5212_FPGA, 
+  PCI_PRODUCT_ATHEROS_AR5212_IBM, 
+     PCI_PRODUCT_3COM_3CRDAG675,     
+    PCI_PRODUCT_3COM2_3CRPAG175,    
+  PCI_PRODUCT_ATHEROS_AR5212_REV2, 
+  PCI_PRODUCT_ATHEROS_AR5212_REV7, 
+  PCI_PRODUCT_ATHEROS_AR5212_REV8, 
+  PCI_PRODUCT_ATHEROS_AR5212_0014, 
+  PCI_PRODUCT_ATHEROS_AR5212_0015, 
+  PCI_PRODUCT_ATHEROS_AR5212_0016, 
+  PCI_PRODUCT_ATHEROS_AR5212_0017, 
+  PCI_PRODUCT_ATHEROS_AR5212_0018, 
+  PCI_PRODUCT_ATHEROS_AR5212_0019, 
+  PCI_PRODUCT_ATHEROS_AR2413,     
+  PCI_PRODUCT_ATHEROS_AR5413,     
+  PCI_PRODUCT_ATHEROS_AR5424,     
-};
-
@@ -160 +160 @@
-/*
- * Calculate transmition time of a frame
-Left here for combatibility, change it in at
-
-
+ Left here for combatibility, change it in ath
+
+l
-ath_hal_computetxtime(struct ath_hal *hal, const AR5K_RATE_TABLE *rates,
-    u_int32_t frame_length, u_int16_t rate_index, AR5K_BOOL short_preamble)
@@ -450 +450 @@
-        hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
-        hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
-AR5K_REG_READ(AR5K_PHY_CHIP_ID) &
-   
+
+       AR5K_REG_READ(AR5K_PHY_CHIP_ID) &
-        hal->ah_radio_5ghz_revision =
-    
-
-(hal->ah_version == AR5K_AR5210)
+       
+
+ (hal->ah_version == AR5K_AR5210) 
-                hal->ah_radio_2ghz_revision = 0;
-        } else {
@@ -467 +467 @@
-
-        /* Identify the radio chip*/
-(hal->ah_version == AR5K_AR5210){
+ (hal->ah_version == AR5K_AR5210)
-                hal->ah_radio = AR5K_RF5110;
-} else {
+else
-                hal->ah_radio = hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112 ?
-                                                        AR5K_RF5111 : AR5K_RF5112;
-        }
-
-        hal->ah_phy = AR5K_PHY(0);
@@ -569 +568 @@
-        AR5K_TRACE;
-
-
+ 
-                /*
-                 * Get channel mode flags
@@ -599 +598 @@
-                } else if (flags & CHANNEL_DYN) {
-                        /* Dynamic OFDM/CCK is not supported by the AR5211 */
-
+ 
-                                mode |= AR5K_PHY_MODE_MOD_CCK;
-else
+ else 
-                                mode |= AR5K_PHY_MODE_MOD_DYN;
-                        }
@@ -620 +619 @@
-
-        else {
-(initial == TRUE)
+ (initial == TRUE) 
-                        /* ...reset hardware */
-                        if (ath5k_hw_nic_reset(hal,
@@ -720 +719 @@
-                AR5K_REG_WRITE(AR5K_PHY(0x20), 0x00010000);
-
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                srev = AR5K_REG_READ(AR5K_PHY(256) >> 28) & 0xf;
-
@@ -815 +814 @@
-         */
-        /*DCU/Antenna selection not available on 5210*/
-(hal->ah_version != AR5K_AR5210)
+ (hal->ah_version != AR5K_AR5210) 
-                if (change_channel == TRUE) {
-                        /*Sequence number for queue 0 -do this for all queues ?*/
@@ -848 +847 @@
-         * 5210 only comes with RF5110
-         */
-(hal->ah_version != AR5K_AR5210)
- {
+ (hal->ah_version != AR5K_AR5210) 
+
-                        phy = AR5K_INI_PHY_5111;
-} else if (hal->ah_radio == AR5K_RF5112) {
+else if (hal->ah_radio == AR5K_RF5112)
-                        phy = AR5K_INI_PHY_5112;
-} 
+
-                        AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio);
-                        *status = AR5K_EINVAL;
@@ -887 +886 @@
-                        break;
-                case CHANNEL_XR:
-(hal->ah_version == AR5K_AR5211)
+ (hal->ah_version == AR5K_AR5211) 
-                                AR5K_PRINTF("XR mode not available on 5211");
-                                return (FALSE);
@@ -908 +907 @@
-                 * do we need that ? Is ath5k_hw_rfregs going to work for 5211 (5111) ?
-                 */
-(hal->ah_version == AR5K_AR5211){
+ (hal->ah_version == AR5K_AR5211)
-                        ath5k_hw_ar5211_rfregs(hal, channel, freq, ee_mode);
-                }
-        }
-
@@ -918 +916 @@
-         */
-        /*For 5212*/
-(hal->ah_version == AR5K_AR5212)
+ (hal->ah_version == AR5K_AR5212) 
-                for (i = 0; i < AR5K_ELEMENTS(ar5212_mode); i++) {
-                        if (ar5212_mode[i].mode_flags == AR5K_INI_FLAG_511X)
@@ -937 +935 @@
-        }
-        /*For 5211*/
-(hal->ah_version == AR5K_AR5211)
+ (hal->ah_version == AR5K_AR5211) 
-                for (i = 0; i < AR5K_ELEMENTS(ar5211_mode); i++) {
-                        AR5K_REG_WAIT(i);
@@ -950 +948 @@
-         */
-        /*For 5212*/
-(hal->ah_version == AR5K_AR5212)
+ (hal->ah_version == AR5K_AR5212) 
-                for (i = 0; i < AR5K_ELEMENTS(ar5212_ini); i++) {
-                        if (change_channel == TRUE &&
@@ -968 +966 @@
-        }
-        /*For 5211*/
-(hal->ah_version == AR5K_AR5211)
+ (hal->ah_version == AR5K_AR5211) 
-                for (i = 0; i < AR5K_ELEMENTS(ar5211_ini); i++) {
-                        if (change_channel == TRUE &&
@@ -981 +979 @@
-        }
-        /*For 5210*/
-
+ 
-                for (i = 0; i < AR5K_ELEMENTS(ar5210_ini); i++) {
-                        if (change_channel == TRUE &&
@@ -1004 +1002 @@
-         * 5211/5212 Specific
-         */
-(hal->ah_version != AR5K_AR5210)
+ (hal->ah_version != AR5K_AR5210) 
-                /*
-                 * Write initial RF gain settings
@@ -1019 +1017 @@
-                 * Set rate duration table on 5212
-                 */
-(hal->ah_version == AR5K_AR5212)
+ (hal->ah_version == AR5K_AR5212) 
-
-                        /*For 802.11b*/
@@ -1094 +1092 @@
-
-                /* Write OFDM timings on 5212*/
-(hal->ah_version == AR5K_AR5212)
+ (hal->ah_version == AR5K_AR5212) 
-                        if (channel->channel_flags & CHANNEL_OFDM) {
-                                u_int32_t coef_scaled, coef_exp, coef_man, ds_coef_exp,
@@ -1199 +1197 @@
-         */
-        /*DCU/Antenna selection not available on 5210*/
-(hal->ah_version != AR5K_AR5210)
+ (hal->ah_version != AR5K_AR5210) 
-                AR5K_REG_WRITE(AR5K_QUEUE_DFS_SEQNUM(0), s_seq);
-                AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, s_ant);
@@ -1214 +1212 @@
-        ath5k_hw_set_opmode(hal);
-        /*PISR/SISR Not available on 5210*/
-(hal->ah_version != AR5K_AR5210)
+ (hal->ah_version != AR5K_AR5210) 
-                AR5K_REG_WRITE(AR5K_PISR, 0xffffffff);
-                AR5K_REG_WRITE(AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES);
@@ -1223 +1221 @@
-         *(passing dma size not available on 5210)
-         */
-(hal->ah_version != AR5K_AR5210)
+ (hal->ah_version != AR5K_AR5210) 
-                AR5K_REG_WRITE_BITS(AR5K_TXCFG, AR5K_TXCFG_SDMAMR,
-                                AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE);
@@ -1246 +1244 @@
-         * 5111/5112 Specific
-         */
-(hal->ah_version != AR5K_AR5210)
+ (hal->ah_version != AR5K_AR5210) 
-                data = AR5K_REG_READ(AR5K_PHY_RX_DELAY) & AR5K_PHY_RX_DELAY_M;
-                data = (channel->channel_flags & CHANNEL_CCK) ?
@@ -1316 +1314 @@
-        for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) {
-                /*No QCU on 5210*/
-(hal->ah_version != AR5K_AR5210){
+ (hal->ah_version != AR5K_AR5210)
-                        AR5K_REG_WRITE_Q(AR5K_QUEUE_QCUMASK(i), i);
-
+
-                if (ath5k_hw_reset_tx_queue(hal, i) == FALSE) {
-                        AR5K_PRINTF("failed to reset TX queue #%d\n", i);
@@ -1327 +1325 @@
-
-        /* Pre-enable interrupts on 5211/5212*/
-(hal->ah_version != AR5K_AR5210)
+ (hal->ah_version != AR5K_AR5210) 
-                ath5k_hw_set_intr(hal, AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_FATAL);
-        }
@@ -1334 +1332 @@
-         * Set RF kill flags if supported by the device (read from the EEPROM)
-         * Disable gpio_intr for now since it results system hang.
-
-
-
+
+
+
+
-                ath5k_hw_set_gpio_input(hal, 0);
-                if ((hal->ah_gpio[0] = ath5k_hw_get_gpio(hal, 0)) == 0)
@@ -1343 +1342 @@
-                        ath5k_hw_set_gpio_intr(hal, 0, 0);
-        }
-
+
-
-        /*
-         * Set the 32MHz reference clock on 5212 phy clock sleep register
-         */
-(hal->ah_version == AR5K_AR5212)
+ (hal->ah_version == AR5K_AR5212) 
-                AR5K_REG_WRITE(AR5K_PHY_SCR, AR5K_PHY_SCR_32MHZ);
-                AR5K_REG_WRITE(AR5K_PHY_SLMT, AR5K_PHY_SLMT_32MHZ);
@@ -1389 +1388 @@
-        AR5K_DELAY(15);
-
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                val &= AR5K_RESET_CTL_CHIP;
-                mask &= AR5K_RESET_CTL_CHIP;
@@ -1576 +1575 @@
-        AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
-
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-
-                tx_queue = AR5K_REG_READ(AR5K_CR);
@@ -1630 +1629 @@
-        AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
-
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                tx_queue = AR5K_REG_READ(AR5K_CR);
-
@@ -1688 +1687 @@
-         */
-        /*5210 doesn't have QCU*/
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                switch (hal->ah_txq[queue].tqi_type) {
-                        case AR5K_TX_QUEUE_DATA:
@@ -1722 +1721 @@
-         * on 5210
-         */
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                switch (hal->ah_txq[queue].tqi_type) {
-                        case AR5K_TX_QUEUE_DATA:
@@ -1781 +1780 @@
-         * Update trigger level on success
-         */
-(hal->ah_version == AR5K_AR5210){
+ (hal->ah_version == AR5K_AR5210)
-                AR5K_REG_WRITE(AR5K_TRIG_LVL, trigger_level);
-} else {
+else
-                AR5K_REG_WRITE_BITS(AR5K_TXCFG,
-                                AR5K_TXCFG_TXFULL, trigger_level);
-        }
-
-        status = TRUE;
@@ -1827 +1825 @@
-         * on 5210
-         */
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                if ((data = AR5K_REG_READ(AR5K_ISR)) == AR5K_INT_NOCARD) {
-                        *interrupt_mask = data;
@@ -1853 +1851 @@
-                *interrupt_mask |= AR5K_INT_TX;
-
-(hal->ah_version != AR5K_AR5210)
+ (hal->ah_version != AR5K_AR5210) 
-                /*HIU = Host Interface Unit (PCI etc)*/
-                if (data & (AR5K_ISR_HIUERR))
@@ -1871 +1869 @@
-
-        /* 
-
-
-
-
+
+
+
+
+
+
-
-        /*
@@ -1933 +1933 @@
-                        AR5K_IMR_TXURN;
-
-(hal->ah_version != AR5K_AR5210)
+ (hal->ah_version != AR5K_AR5210) 
-                if (new_mask & AR5K_INT_FATAL) {
-                        int_mask |= AR5K_IMR_HIUERR;
@@ -1973 +1973 @@
-         * possible radar activity.
-         */
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                if (enable == TRUE) {
-                        AR5K_REG_ENABLE_BITS(AR5K_IMR,
@@ -2030 +2030 @@
-         * Initialize EEPROM access
-         */
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                AR5K_REG_ENABLE_BITS(AR5K_PCICFG, AR5K_PCICFG_EEAE);
-                (void)AR5K_REG_READ(AR5K_EEPROM_BASE + (4 * offset));
@@ -2069 +2069 @@
-         */
-
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                AR5K_REG_ENABLE_BITS(AR5K_PCICFG, AR5K_PCICFG_EEAE);
-        } else {
@@ -2079 +2079 @@
-         */
-
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                AR5K_REG_WRITE(AR5K_EEPROM_BASE + (4 * offset), data);
-        } else {
@@ -2171 +2171 @@
-            (ee->ee_ant_control[mode][0] << 4) | 0x1;
-        hal->ah_antenna[mode][AR5K_ANT_FIXED_A] =
-ee->ee_ant_control[mode][1] 
-
+ ee->ee_ant_control[mode][1]       
+        
-            (ee->ee_ant_control[mode][3] << 12) |
-            (ee->ee_ant_control[mode][4] << 18) |
-            (ee->ee_ant_control[mode][5] << 24);
-        hal->ah_antenna[mode][AR5K_ANT_FIXED_B] =
-ee->ee_ant_control[mode][6] 
-
+ ee->ee_ant_control[mode][6]       
+        
-            (ee->ee_ant_control[mode][8] << 12) |
-            (ee->ee_ant_control[mode][9] << 18) |
@@ -2570 +2570 @@
-        ee_header = hal->ah_capabilities.cap_eeprom.ee_header;
-
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                /*
-                 * Set radio capabilities
@@ -2624 +2624 @@
-
-        /* Set number of supported TX queues */
-(hal->ah_version == AR5K_AR5210){
+ (hal->ah_version == AR5K_AR5210)
-                hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES_NOQCU;
-} else {
+else
-                hal->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
-        }
-
-        return (TRUE);
@@ -2693 +2692 @@
-         * Set Beacon Control Register on 5210
-         */
-(hal->ah_version == AR5K_AR5210){
+ (hal->ah_version == AR5K_AR5210)
-                AR5K_REG_WRITE(AR5K_BCR, beacon_reg);
-        }
-
-        return;
@@ -2756 +2754 @@
-         * Set simple BSSID mask on 5212
-         */
-(hal->ah_version == AR5K_AR5212)
+ (hal->ah_version == AR5K_AR5212) 
-                AR5K_REG_WRITE(AR5K_BSS_IDM0, 0xfffffff);
-                AR5K_REG_WRITE(AR5K_BSS_IDM1, 0xfffffff);
@@ -2791 +2789 @@
-        AR5K_TRACE;
-
-(hal->ah_version == AR5K_AR5212){  
+ (hal->ah_version == AR5K_AR5212) {
-
-                low_id = AR5K_LOW_ID(mask);
@@ -2800 +2798 @@
-
-                return (TRUE); 
- {
+
-                return (FALSE);
-        }
-}
-
@@ -2854 +2851 @@
-
-        AR5K_TRACE;
- {
+
-            return (FALSE);
-} else if (index >= 32) {
+else if (index >= 32)
-            AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER1,
-                (1 << (index - 32)));
-} else {
+else
-            AR5K_REG_ENABLE_BITS(AR5K_MCAST_FILTER0,
-                (1 << index));
-        }
-
-        return (TRUE);
@@ -2875 +2871 @@
-
-        AR5K_TRACE;
- {
+
-            return (FALSE);
-} else if (index >= 32) {
+else if (index >= 32)
-            AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER1,
-                (1 << (index - 32)));
-} else {
+else
-            AR5K_REG_DISABLE_BITS(AR5K_MCAST_FILTER0,
-                (1 << index));
-        }
-
-        return (TRUE);
@@ -2900 +2895 @@
-
-        /*Radar detection for 5212*/
-(hal->ah_version == AR5K_AR5212)
+ (hal->ah_version == AR5K_AR5212) 
-                data = AR5K_REG_READ(AR5K_PHY_ERR_FIL);
-
@@ -2924 +2919 @@
-
-        /* Set PHY error filter register on 5212*/
-(hal->ah_version == AR5K_AR5212)
+ (hal->ah_version == AR5K_AR5212) 
-                if (filter & AR5K_RX_FILTER_PHYRADAR)
-                        data |= AR5K_PHY_ERR_FIL_RADAR;
@@ -2935 +2930 @@
-         * The AR5210 uses promiscous mode to detect radar activity
-         */
-
-(filter & AR5K_RX_FILTER_PHYRADAR))
+ 
+               (filter & AR5K_RX_FILTER_PHYRADAR)) 
-                filter &= ~AR5K_RX_FILTER_PHYRADAR;
-                filter |= AR5K_RX_FILTER_PROM;
@@ -2942 +2937 @@
-
-        /*Zero length DMA*/
- {
+
-                AR5K_REG_ENABLE_BITS(AR5K_RXCFG,
-                                AR5K_RXCFG_ZLFDMA);
-} else {
+else
-                AR5K_REG_DISABLE_BITS(AR5K_RXCFG,
-                                AR5K_RXCFG_ZLFDMA);
-        }
-
-        /*Write RX Filter register*/
@@ -2954 +2948 @@
-
-        /*Write PHY error filter register on 5212*/
-(hal->ah_version == AR5K_AR5212){
+ (hal->ah_version == AR5K_AR5212)
-                AR5K_REG_WRITE(AR5K_PHY_ERR_FIL, data);
-        }
-
-}
@@ -3012 +3005 @@
-        switch (hal->ah_op_mode) {
-        case AR5K_M_STA:
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                        timer1 = 0xffffffff;
-                        timer2 = 0xffffffff;
@@ -3137 +3130 @@
-         * Set enhanced sleep registers on 5212
-         */
-(hal->ah_version == AR5K_AR5212)
+ (hal->ah_version == AR5K_AR5212) 
-                if ((state->bs_sleep_duration > state->bs_interval) &&
-                (roundup(state->bs_sleep_duration, interval) ==
@@ -3206 +3199 @@
-
-        /* 5210 doesn't have QCU*/
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                /*
-                 * Wait for beaconn queue to finish by checking
@@ -3255 +3248 @@
-
-        /* Reset profile count registers on 5212*/
-(hal->ah_version == AR5K_AR5212)
+ (hal->ah_version == AR5K_AR5212) 
-                AR5K_REG_WRITE(AR5K_PROFCNT_TX, 0);
-                AR5K_REG_WRITE(AR5K_PROFCNT_RX, 0);
@@ -3375 +3368 @@
-
-        /* Set NULL encryption on non-5210*/
-(hal->ah_version != AR5K_AR5210){
+ (hal->ah_version != AR5K_AR5210)
-                AR5K_REG_WRITE(AR5K_KEYTABLE_TYPE(entry),
-                                AR5K_KEYTABLE_TYPE_NULL);
-        }
-
-        return (FALSE); /*????*/
@@ -3499 +3491 @@
-         */
-        /*5210 only has 2 queues*/
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                switch (queue_type) {
-                        case AR5K_TX_QUEUE_DATA:
@@ -3512 +3504 @@
-                }
-        } else {
-(queue_type)
+ (queue_type) 
-                        case AR5K_TX_QUEUE_DATA:
-                                for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
-
-
+
+
+
-                                        if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
-                                                return (-1);
@@ -3531 +3524 @@
-                                break;
-                        case AR5K_TX_QUEUE_XR_DATA:
-
+ 
-                                        AR5K_PRINTF("XR data queues only supported in 5212!");
-                                queue = AR5K_TX_QUEUE_ID_XR_DATA;
@@ -3636 +3629 @@
-                return (TRUE);
-
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                /* Only handle data queues, others will be ignored */
-                if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
@@ -3658 +3651 @@
-        /*XR is only supported on 5212*/
-        if (IS_CHAN_XR(hal->ah_current_channel)
-
+               
-                cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR;
-                cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR;
@@ -3664 +3657 @@
-        /*B mode is not supported on 5210*/
-        } else if (IS_CHAN_B(hal->ah_current_channel)
-
+               
-                cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B;
-                cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B;
@@ -3696 +3689 @@
-
-        /*No QCU/DCU [5210]*/
-(hal->ah_version == AR5K_AR5210)
+ (hal->ah_version == AR5K_AR5210) 
-                AR5K_REG_WRITE(AR5K_NODCU_RETRY_LMT,
-                        (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
@@ -3844 +3837 @@
-        AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
-
-
-
-
+
+
-
-        return (AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT);
@@ -3861 +3853 @@
-                return (FALSE);
-
-(hal->ah_version == AR5K_AR5210){
+ (hal->ah_version == AR5K_AR5210)
-                AR5K_REG_WRITE(AR5K_SLOT_TIME,
-                        ath5k_hw_htoclock(slot_time, hal->ah_turbo));
-} else {
+else
-                AR5K_REG_WRITE(AR5K_DCU_GBL_IFS_SLOT, slot_time);
-        }
-
-        return (TRUE);
@@ -3878 +3869 @@
-{
-        AR5K_TRACE;
-(hal->ah_version == AR5K_AR5210){
+ (hal->ah_version == AR5K_AR5210)
-                return (ath5k_hw_clocktoh(AR5K_REG_READ(AR5K_SLOT_TIME) &
-                    0xffff, hal->ah_turbo));
-} else {
+else
-                return (AR5K_REG_READ(AR5K_DCU_GBL_IFS_SLOT) & 0xffff);
-        }
-}
-
@@ -3925 +3915 @@
-        /*Verify packet length*/
-        if ((tx_desc->tx_control_0 = (packet_length &
-
+               
-                return (FALSE);
-        /*
@@ -3931 +3921 @@
-         * XXX: I only found that on 5210 code, does it work on 5211 ?
-         */
-(hal->ah_version == AR5K_AR5210){
+ (hal->ah_version == AR5K_AR5210)
-                if ((tx_desc->tx_control_0 = (header_length &
-
+               
-                        return (FALSE);
-        }
-
-        /*Diferences between 5210-5211*/
-(hal->ah_version == AR5K_AR5210)
-(type)
+ (hal->ah_version == AR5K_AR5210) 
+ (type) 
-                        case AR5K_PKT_TYPE_BEACON:
-                        case AR5K_PKT_TYPE_PROBE_RESP:
@@ -3987 +3976 @@
-         */
-        if ((hal->ah_version == AR5K_AR5210) &&
-
+               
-                tx_desc->tx_control_1 |=
-                        rtscts_duration & AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
@@ -4024 +4013 @@
-        /* Setup status descriptor */
-        if ((tx_desc->tx_control_0 = (packet_length &
-
+               
-                return (FALSE);
-
@@ -4090 +4079 @@
-        struct ath5k_hw_4w_tx_desc *tx_desc;
-
-(hal->ah_version == AR5K_AR5212)
+ (hal->ah_version == AR5K_AR5212) 
-                tx_desc = (struct ath5k_hw_4w_tx_desc*)&desc->ds_ctl0;
-
@@ -4111 +4100 @@
-                return (TRUE);
-        }
+
-        return(FALSE);
-}
@@ -4130 +4120 @@
-        /* Validate segment length and initialize the descriptor */
-        if ((tx_desc->tx_control_1 = (segment_length &
-
+               
-                return (FALSE);
-
@@ -4163 +4153 @@
-        /* Validate segment length and initialize the descriptor */
-        if ((tx_desc->tx_control_1 = (segment_length &
-
+               
-                return (FALSE);
-
@@ -4217 +4207 @@
-
-        if ((tx_status->tx_status_0 &
-
+               
-                if (tx_status->tx_status_0 &
-
+               
-                        desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY;
-
-                if (tx_status->tx_status_0 &
-
+               
-                        desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO;
-
-                if (tx_status->tx_status_0 &
-
+               
-                        desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT;
-        }
@@ -4274 +4264 @@
-
-        switch (AR5K_REG_MS(tx_status->tx_status_1,
-    
+       
-        case 0:
-                desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 &
@@ -4402 +4392 @@
-         */
-        if (rx_status->rx_status_1 &
- {
+
-                desc->ds_us.rx.rs_keyix =
-                    AR5K_REG_MS(rx_status->rx_status_1,
-                        AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX);
-} else {