Changeset 3868

Timestamp:

10/08/08 18:04:10 (3 months ago)

Author:

mickflemm

Message:

• Add support for RF2413
  
• Comment out RF5112 for now (working on an abstract way to handle different table formats etc)
  

Files:

• ath_info/trunk/ath_info.c (modified) (32 diffs)
• ath_info/trunk/eeprom.h (added)

ath_info/trunk/ath_info.c

@@ -29 +29 @@
-#include <endian.h>
-#include <byteswap.h>
+#include "eeprom.h"
-
-#undef ARRAY_SIZE
@@ -65 +66 @@
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-static const struct ath5k_srev_name ath5k_mac_names[] = {
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-static const struct ath5k_srev_name ath5k_phy_names[] = {
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@@ -191 +212 @@
-
-/*
- * Common AR5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE)
- */
-#define AR5K_EEPROM_MAGIC3              0x003d  /* EEPROM Magic number (old layout) */
-#define AR5K_EEPROM_MAGIC5              0x0000  /* EEPROM Magic number (new layout) */
-#define AR5K_EEPROM_MAGIC       (mac_revision < AR5K_SREV_MAC_AR5416 ? \
-                                 AR5K_EEPROM_MAGIC3 : AR5K_EEPROM_MAGIC5)
-#define AR5K_EEPROM_MAGIC_VALUE3        0x5aa5
-#define AR5K_EEPROM_MAGIC_VALUE5        0xa55a
-#define AR5K_EEPROM_MAGIC_VALUE (mac_revision < AR5K_SREV_MAC_AR5416 ? \
-                                 AR5K_EEPROM_MAGIC_VALUE3 : AR5K_EEPROM_MAGIC_VALUE5)
-#define AR5K_EEPROM_MAGIC_5212          0x0000145c      /* 5212 */
-#define AR5K_EEPROM_MAGIC_5211          0x0000145b      /* 5211 */
-#define AR5K_EEPROM_MAGIC_5210          0x0000145a      /* 5210 */
-
-#define AR5K_EEPROM_PROTECT             0x003f  /* EEPROM protect status */
-#define AR5K_EEPROM_PROTECT_RD_0_31     0x0001  /* Read protection bit for offsets 0x0 - 0x1f */
-#define AR5K_EEPROM_PROTECT_WR_0_31     0x0002  /* Write protection bit for offsets 0x0 - 0x1f */
-#define AR5K_EEPROM_PROTECT_RD_32_63    0x0004  /* 0x20 - 0x3f */
-#define AR5K_EEPROM_PROTECT_WR_32_63    0x0008
-#define AR5K_EEPROM_PROTECT_RD_64_127   0x0010  /* 0x40 - 0x7f */
-#define AR5K_EEPROM_PROTECT_WR_64_127   0x0020
-#define AR5K_EEPROM_PROTECT_RD_128_191  0x0040  /* 0x80 - 0xbf (regdom) */
-#define AR5K_EEPROM_PROTECT_WR_128_191  0x0080
-#define AR5K_EEPROM_PROTECT_RD_192_207  0x0100  /* 0xc0 - 0xcf */
-#define AR5K_EEPROM_PROTECT_WR_192_207  0x0200
-#define AR5K_EEPROM_PROTECT_RD_208_223  0x0400  /* 0xd0 - 0xdf */
-#define AR5K_EEPROM_PROTECT_WR_208_223  0x0800
-#define AR5K_EEPROM_PROTECT_RD_224_239  0x1000  /* 0xe0 - 0xef */
-#define AR5K_EEPROM_PROTECT_WR_224_239  0x2000
-#define AR5K_EEPROM_PROTECT_RD_240_255  0x4000  /* 0xf0 - 0xff */
-#define AR5K_EEPROM_PROTECT_WR_240_255  0x8000
-#define AR5K_EEPROM_REG_DOMAIN          0x00bf  /* EEPROM regdom */
-#define AR5K_EEPROM_INFO_BASE           0x00c0  /* EEPROM header */
-#define AR5K_EEPROM_INFO_MAX            (0x400 - AR5K_EEPROM_INFO_BASE)
-#define AR5K_EEPROM_INFO_CKSUM          0xffff
-#define AR5K_EEPROM_INFO(_n)            (AR5K_EEPROM_INFO_BASE + (_n))
-
-#define AR5K_EEPROM_VERSION             AR5K_EEPROM_INFO(1)     /* EEPROM Version */
-#define AR5K_EEPROM_VERSION_3_0         0x3000  /* No idea what's going on before this version */
-#define AR5K_EEPROM_VERSION_3_1         0x3001  /* ob/db values for 2GHz (AR5211_rfregs) */
-#define AR5K_EEPROM_VERSION_3_2         0x3002  /* different frequency representation (eeprom_bin2freq) */
-#define AR5K_EEPROM_VERSION_3_3         0x3003  /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */
-#define AR5K_EEPROM_VERSION_3_4         0x3004  /* has ee_i_gain ee_cck_ofdm_power_delta (eeprom_read_modes) */
-#define AR5K_EEPROM_VERSION_4_0         0x4000  /* has ee_misc*, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */
-#define AR5K_EEPROM_VERSION_4_1         0x4001  /* has ee_margin_tx_rx (eeprom_init) */
-#define AR5K_EEPROM_VERSION_4_2         0x4002  /* has ee_cck_ofdm_gain_delta (eeprom_init) */
-#define AR5K_EEPROM_VERSION_4_3         0x4003
-#define AR5K_EEPROM_VERSION_4_4         0x4004
-#define AR5K_EEPROM_VERSION_4_5         0x4005
-#define AR5K_EEPROM_VERSION_4_6         0x4006  /* has ee_scaled_cck_delta */
-#define AR5K_EEPROM_VERSION_4_7         0x3007
-
-#define AR5K_EEPROM_MODE_11A            0
-#define AR5K_EEPROM_MODE_11B            1
-#define AR5K_EEPROM_MODE_11G            2
-
-#define AR5K_EEPROM_HDR                 AR5K_EEPROM_INFO(2)     /* Header that contains the device caps */
-#define AR5K_EEPROM_HDR_11A(_v)         (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
-#define AR5K_EEPROM_HDR_11B(_v)         (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
-#define AR5K_EEPROM_HDR_11G(_v)         (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
-#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v)  (((_v) >> 3) & 0x1)     /* Disable turbo for 2GHz (?) */
-#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v)  (((_v) >> 4) & 0x7f)    /* Max turbo power for a/XR mode (eeprom_init) */
-#define AR5K_EEPROM_HDR_DEVICE(_v)      (((_v) >> 11) & 0x7)
-#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v)  (((_v) >> 15) & 0x1)    /* Disable turbo for 5GHz (?) */
-#define AR5K_EEPROM_HDR_RFKILL(_v)      (((_v) >> 14) & 0x1)    /* Device has RFKill support */
-
-/* Misc values available since EEPROM 4.0 */
-#define AR5K_EEPROM_MISC0               AR5K_EEPROM_INFO(4)
-#define AR5K_EEPROM_EARSTART(_v)        ((_v) & 0xfff)
-#define AR5K_EEPROM_HDR_XR2_DIS(_v)     (((_v) >> 12) & 0x1)
-#define AR5K_EEPROM_HDR_XR5_DIS(_v)     (((_v) >> 13) & 0x1)
-#define AR5K_EEPROM_EEMAP(_v)           (((_v) >> 14) & 0x3)
-#define AR5K_EEPROM_MISC1               AR5K_EEPROM_INFO(5)
-#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
-#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
-
-#define AR5K_EEPROM_RFKILL_GPIO_SEL     0x0000001c
-#define AR5K_EEPROM_RFKILL_GPIO_SEL_S   2
-#define AR5K_EEPROM_RFKILL_POLARITY     0x00000002
-#define AR5K_EEPROM_RFKILL_POLARITY_S   1
-
-/* Newer EEPROMs are using a different offset */
-#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
-        (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
-
-#define AR5K_EEPROM_ANT_GAIN(_v)        AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
-#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v)   ((int8_t)(((_v) >> 8) & 0xff))
-#define AR5K_EEPROM_ANT_GAIN_2GHZ(_v)   ((int8_t)((_v) & 0xff))
-
-/* calibration settings */
-#define AR5K_EEPROM_MODES_11A(_v)       AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
-#define AR5K_EEPROM_MODES_11B(_v)       AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
-#define AR5K_EEPROM_MODES_11G(_v)       AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
-#define AR5K_EEPROM_CTL(_v)             AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128)     /* Conformance test limits */
-#define AR5K_EEPROM_CHANNELS_5GHZ(_v)   AR5K_EEPROM_OFF(_v, 0x0100, 0x0150)     /* List of calibrated 5GHz chans */
-#define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_CHANNELS_5GHZ(_v) + 0x0055, 0x0000)
-#define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_CHANNELS_5GHZ(_v) + 0x0065, 0x0010)
-#define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_CHANNELS_5GHZ(_v) + 0x0069, 0x0014)
-
-/* [3.1 - 3.3] */
-#define AR5K_EEPROM_OBDB0_2GHZ          0x00ec
-#define AR5K_EEPROM_OBDB1_2GHZ          0x00ed
-
-/*
- * EEPROM data register
- */
@@ -326 +243 @@
- */
-#define AR5K_EEPROM_CFG 0x6010
-
-/* Some EEPROM defines */
-#define AR5K_EEPROM_EEP_SCALE           100
-#define AR5K_EEPROM_EEP_DELTA           10
-#define AR5K_EEPROM_N_MODES             3
-#define AR5K_EEPROM_N_5GHZ_CHAN         10
-#define AR5K_EEPROM_N_2GHZ_CHAN         3
-#define AR5K_EEPROM_MAX_CHAN            10
-#define AR5K_EEPROM_N_PCDAC             11
-#define AR5K_EEPROM_N_TEST_FREQ         8
-#define AR5K_EEPROM_N_EDGES             8
-#define AR5K_EEPROM_N_INTERCEPTS        11
-#define AR5K_EEPROM_FREQ_M(_v)          AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
-#define AR5K_EEPROM_PCDAC_M             0x3f
-#define AR5K_EEPROM_PCDAC_START         1
-#define AR5K_EEPROM_PCDAC_STOP          63
-#define AR5K_EEPROM_PCDAC_STEP          1
-#define AR5K_EEPROM_NON_EDGE_M          0x40
-#define AR5K_EEPROM_CHANNEL_POWER       8
-#define AR5K_EEPROM_N_OBDB              4
-#define AR5K_EEPROM_OBDB_DIS            0xffff
-#define AR5K_EEPROM_CHANNEL_DIS         0xff
-#define AR5K_EEPROM_SCALE_OC_DELTA(_x)  (((_x) * 2) / 10)
-#define AR5K_EEPROM_N_CTLS(_v)          AR5K_EEPROM_OFF(_v, 16, 32)
-#define AR5K_EEPROM_MAX_CTLS            32
-#define AR5K_EEPROM_N_XPD_PER_CHANNEL   4
-#define AR5K_EEPROM_N_XPD0_POINTS       4
-#define AR5K_EEPROM_N_XPD3_POINTS       3
-#define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
-#define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
-#define AR5K_EEPROM_POWER_M             0x3f
-#define AR5K_EEPROM_POWER_MIN           0
-#define AR5K_EEPROM_POWER_MAX           3150
-#define AR5K_EEPROM_POWER_STEP          50
-#define AR5K_EEPROM_POWER_TABLE_SIZE    64
-#define AR5K_EEPROM_N_POWER_LOC_11B     4
-#define AR5K_EEPROM_N_POWER_LOC_11G     6
-#define AR5K_EEPROM_I_GAIN              10
-#define AR5K_EEPROM_CCK_OFDM_DELTA      15
-#define AR5K_EEPROM_N_IQ_CAL            2
-
-enum ath5k_ant_setting {
-        AR5K_ANT_VARIABLE       = 0,    /* variable by programming */
-        AR5K_ANT_FIXED_A        = 1,    /* fixed to 11a frequencies */
-        AR5K_ANT_FIXED_B        = 2,    /* fixed to 11b frequencies */
-        AR5K_ANT_MAX            = 3,
-};
-
-/* Per channel calibration data, used for power table setup */
-struct ath5k_chan_pcal_info {
-        u_int16_t       freq; /* Frequency */
-        /* Power levels in dBm * 4 units */
-        int16_t         pwr_x0[AR5K_EEPROM_N_XPD0_POINTS];
-        int16_t         pwr_x3[AR5K_EEPROM_N_XPD3_POINTS];
-        /* PCDAC tables in dBm * 2 units */
-        u_int16_t       pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS];
-        u_int16_t       pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS];
-        /* Max available power */
-        u_int16_t       max_pwr;
-};
-
-/* Per rate calibration data for each mode, used for power table setup */
-struct ath5k_rate_pcal_info {
-        u_int16_t       freq; /* Frequency */
-        /* Power level for 6-24Mbit/s rates */
-        u_int16_t       target_power_6to24;
-        /* Power level for 36Mbit rate */
-        u_int16_t       target_power_36;
-        /* Power level for 48Mbit rate */
-        u_int16_t       target_power_48;
-        /* Power level for 54Mbit rate */
-        u_int16_t       target_power_54;
-};
-
-/* EEPROM calibration data */
-struct ath5k_eeprom_info {
-
-        /* Header information */
-        u_int16_t       ee_magic;
-        u_int16_t       ee_protect;
-        u_int16_t       ee_regdomain;
-        u_int16_t       ee_version;
-        u_int16_t       ee_header;
-        u_int16_t       ee_ant_gain;
-        u_int16_t       ee_misc0;
-        u_int16_t       ee_misc1;
-        u_int16_t       ee_cck_ofdm_gain_delta;
-        u_int16_t       ee_cck_ofdm_power_delta;
-        u_int16_t       ee_scaled_cck_delta;
-
-        /* Used for tx thermal adjustment (eeprom_init, rfregs) */
-        u_int16_t       ee_tx_clip;
-        u_int16_t       ee_pwd_84;
-        u_int16_t       ee_pwd_90;
-        u_int16_t       ee_gain_select;
-
-        /* RF Calibration settings (reset, rfregs) */
-        u_int16_t       ee_i_cal[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_q_cal[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_fixed_bias[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_turbo_max_power[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_xr_power[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_switch_settling[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_ant_tx_rx[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
-        u_int16_t       ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
-        u_int16_t       ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
-        u_int16_t       ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_thr_62[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_xlna_gain[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_xpd[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_x_gain[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_i_gain[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
-
-        /* Power calibration data */
-        u_int16_t       ee_false_detect[AR5K_EEPROM_N_MODES];
-        u_int16_t       ee_cal_piers_a;
-        struct ath5k_chan_pcal_info     ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN];
-        u_int16_t       ee_cal_piers_b;
-        struct ath5k_chan_pcal_info     ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN];
-        u_int16_t       ee_cal_piers_g;
-        struct ath5k_chan_pcal_info     ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN];
-        /* Per rate target power levels */
-        u_int16_t       ee_rate_target_pwr_num_a;
-        struct ath5k_rate_pcal_info     ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN];
-        u_int16_t       ee_rate_target_pwr_num_b;
-        struct ath5k_rate_pcal_info     ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN];
-        u_int16_t       ee_rate_target_pwr_num_g;
-        struct ath5k_rate_pcal_info     ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN];
-
-        /* Conformance test limits (Unused) */
-        u_int16_t       ee_ctls;
-        u_int16_t       ee_ctl[AR5K_EEPROM_MAX_CTLS];
-
-        /* Noise Floor Calibration settings */
-        int16_t         ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
-        int8_t          ee_adc_desired_size[AR5K_EEPROM_N_MODES];
-        int8_t          ee_pga_desired_size[AR5K_EEPROM_N_MODES];
-
-        u_int32_t       ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
-};
-
-/*
@@ -581 +354 @@
-                AR5K_REG_WRITE(AR5K_PHY(0x20), 0x00010000);
-
-MAC_
+
-                srev = AR5K_REG_READ(AR5K_PHY(256) >> 28) & 0xf;
-
@@ -720 +493 @@
-        AR5K_EEPROM_READ(o++, val);
-        ee->ee_switch_settling[mode]    = (val >> 8) & 0x7f;
-nt
+tn
-        ee->ee_ant_control[mode][i]     = (val << 4) & 0x3f;
-
@@ -776 +549 @@
-        int ret;
-
+        switch (mode){
+        case AR5K_EEPROM_MODE_11A:
+                AR5K_EEPROM_READ(o++, val);
+                ee->ee_adc_desired_size[mode]   = (int8_t)((val >> 8) & 0xff);
+                ee->ee_ob[mode][3]              = (val >> 5) & 0x7;
+                ee->ee_db[mode][3]              = (val >> 2) & 0x7;
+                ee->ee_ob[mode][2]              = (val << 1) & 0x7;
+
+                AR5K_EEPROM_READ(o++, val);
+                ee->ee_ob[mode][2]              |= (val >> 15) & 0x1;
+                ee->ee_db[mode][2]              = (val >> 12) & 0x7;
+                ee->ee_ob[mode][1]              = (val >> 9) & 0x7;
+                ee->ee_db[mode][1]              = (val >> 6) & 0x7;
+                ee->ee_ob[mode][0]              = (val >> 3) & 0x7;
+                ee->ee_db[mode][0]              = val & 0x7;
+                break;
+        case AR5K_EEPROM_MODE_11B:
+                AR5K_EEPROM_READ(o++, val);
+                ee->ee_adc_desired_size[mode]   = (int8_t)((val >> 8) & 0xff);
+                ee->ee_ob[mode][1]              = (val >> 4) & 0x7;
+                ee->ee_db[mode][1]              = val & 0x7;
+                break;
+        case AR5K_EEPROM_MODE_11G:
+                AR5K_EEPROM_READ(o++, val);
+                ee->ee_adc_desired_size[mode]   = (signed short int)((val >> 8) & 0xff);
+                ee->ee_ob[mode][1]              = (val >> 4) & 0x7;
+                ee->ee_db[mode][1]              = val & 0x7;
+                break;
+        }
+
-        AR5K_EEPROM_READ(o++, val);
-        ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
@@ -828 +631 @@
-                ee->ee_i_gain[mode] |= (val << 3) & 0x38;
-
-
+ {
-                        ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
+
+                        if (ee->ee_version >= AR5K_EEPROM_VERSION_4_6)
+                                ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
+                }
-        }
-
@@ -838 +645 @@
-        }
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-
-        /* return new offset */
@@ -864 +794 @@
- * interpolate (in order to create the table for any channel).
- */
-
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+
+
+
+
+
-        unsigned int i, c;
-        int ret;
-        u_int16_t val;
-
+_rf5112
-        u_int16_t cal_piers;
-
-        switch (mode) {
-        case AR5K_EEPROM_MODE_11A:
+                /*
+                 * Read 5GHz EEPROM channels
+                 */
+                offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
+                ee->ee_cal_piers_a = 0;
+                for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
+                        AR5K_EEPROM_READ(offset++, val);
+
+                        if ((val & 0xff) == 0)
+                                break;
+
+                        ee->ee_pwr_cal_a[i].freq =
+                                ath5k_eeprom_bin2freq(ee, val & 0xff,
+                                                AR5K_EEPROM_MODE_11A);
+                        ee->ee_cal_piers_a++;
+
+                        if (((val >> 8) & 0xff) == 0)
+                                break;
+
+                        ee->ee_pwr_cal_a[++i].freq =
+                                ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff,
+                                                        AR5K_EEPROM_MODE_11A);
+                        ee->ee_cal_piers_a++;
+
+                }
+                offset = AR5K_EEPROM_GROUPS_START(ee->ee_version) +
+                                                AR5K_EEPROM_GROUP2_OFFSET;
-                chan_pcal_info = ee->ee_pwr_cal_a;
-                cal_piers = ee->ee_cal_piers_a;
-                break;
-        case AR5K_EEPROM_MODE_11B:
+                offset = AR5K_EEPROM_GROUPS_START(ee->ee_version) +
+                                                AR5K_EEPROM_GROUP3_OFFSET;
-                chan_pcal_info = ee->ee_pwr_cal_b;
-                cal_piers = ee->ee_cal_piers_b;
-                break;
-        case AR5K_EEPROM_MODE_11G:
+                offset = AR5K_EEPROM_GROUPS_START(ee->ee_version) +
+                                                AR5K_EEPROM_GROUP4_OFFSET;
-                chan_pcal_info = ee->ee_pwr_cal_g;
-                cal_piers = ee->ee_cal_piers_g;
@@ -892 +854 @@
-
-        for (i = 0; i < cal_piers; i++) {
-
+
+
+
-                for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
-
+ffset
-                        chan_pcal_info[i].pwr_x0[c] = (val & 0xff);
-                        chan_pcal_info[i].pwr_x0[++c] = ((val >> 8) & 0xff);
-                }
-
-
-
+
+
+
+
-                chan_pcal_info[i].pcdac_x0[1] = (val & 0x1f);
-                chan_pcal_info[i].pcdac_x0[2] = ((val >> 5) & 0x1f);
-                chan_pcal_info[i].pcdac_x0[3] = ((val >> 10) & 0x1f);
-
-No idea what these power levels are for (4 xpds ?)
-  I got zeroes on my card and the EEPROM info
-  dumps we found on the net also have weird values
-
+Power values in dBm * 4
+* for the higher xpd gain curve
+* (18 dBm -> lower output power)
+ffset
-                chan_pcal_info[i].pwr_x3[0] = (val & 0xff);
-                chan_pcal_info[i].pwr_x3[1] = ((val >> 8) & 0xff);
-
-
+ffset
-                chan_pcal_info[i].pwr_x3[2] = (val & 0xff);
-
-
-
-
-
+
+
+
+
-                chan_pcal_info[i].pcdac_x3[0] = 20;
-                chan_pcal_info[i].pcdac_x3[1] = 35;
-                chan_pcal_info[i].pcdac_x3[2] = 63;
-
-
-
+
+
+
+
+
+
+
+
+
-
-                /* Recreate pcdac_x0 table for this channel using pcdac steps */
@@ -932 +904 @@
-        }
-
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